Embodiments of the invention described herein generally relate to forward error correction (FEC) and, more specifically, to low-density parity-check (LDPC) encoding and decoding for satellite communications.
Forward error correction (FEC) is a method of transmitting redundant information with transmitted data to allow a receiver to reconstruct the data if there is an error in the transmission. At a transmitter, a structured redundancy may be added in the form of some parity bits by encoding the data. This structured redundancy may be exploited at the receiver by decoding to correct any errors introduced during transmission.
Some FEC coding schemes incorporate iterative decoding by a decoder. Turbo codes and LDPC codes are examples of coding schemes that may be iteratively decoded. However, because of the complexity of these coding schemes, there may be very significant memory and processing resources required in some implementations of the decoder. LDPC edge memory, in particular, can have a very substantial footprint in many traditional LDPC decoder designs. There is, thus, a need in the art to reduce the size of the edge memory while maintaining performance.